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general description the MAX9121/max9122 quad low-voltage differential sig- naling (lvds) differential line receivers are ideal for appli- cations requiring high data rates, low power, and low noise. the MAX9121/max9122 are guaranteed to receive data at speeds up to 500mbps (250mhz) over controlled- impedance media of approximately 100 ? . the transmis- sion media may be printed circuit (pc) board traces or cables. the MAX9121/max9122 accept four lvds differential inputs and translate them to lvcmos outputs. the max9122 features integrated parallel termination resis- tors (nominally 107 ? ), which eliminate the requirement for four discrete termination resistors and reduce stub lengths. the MAX9121 inputs are high impedance and require an external termination resistor when used in a point-to-point connection. the devices support a wide common-mode input range of 0.05v to 2.35v, allowing for ground potential differences and common-mode noise between the driver and the receiver. a fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or parallel terminated. the en and en inputs con- trol the high-impedance output. the enables are common to all four receivers. inputs conform to the ansi tia/eia- 644 lvds standard. flow-through pinout simplifies pc board layout and reduces crosstalk by separating the lvds inputs and lvcmos outputs. the MAX9121/ max9122 operate from a single +3.3v supply, and are specified for operation from -40? to +85?. these devices are available in 16-pin tssop and so packages. refer to the max9123 data sheet for a quad lvds line dri- ver with flow-through pinout. applications digital copiers laser printers cellular phone base stations add/drop muxes digital cross-connects dslams network switches/routers backplane interconnect clock distribution ____________________________features integrated termination eliminates four external resistors (max9122) flow-through pinout simplifies pc board layout reduces crosstalk pin compatible with ds90lv048a guaranteed 500mbps data rate 300ps pulse skew (max) conform to ansi tia/eia-644 lvds standard single +3.3v supply fail-safe circuit MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout ________________________________________________________________ maxim integrated products 1 typical application circuit 19-1909; rev 0; 6/01 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp. range pin-package MAX9121 eue -40 c to +85 c 16 tssop MAX9121ese -40 c to +85 c 16 so max9122 eue -40 c to +85 c 16 tssop max9122ese -40 c to +85 c 16 so pin configuration appears at end of data sheet. max9123 max9122 t x t x t x t x r x r x r x r x 107 ? 107 ? 107 ? 107 ? 100 ? shielded twisted cable or microstrip pc board traces lvds signals lvttl/lvcmos data output lvttl/lvcmos data input
v cc to gnd ...........................................................-0.3v to +4.0v in_+, in_- to gnd .................................................-0.3v to +4.0v en, en to gnd ...........................................-0.3v to (v cc + 0.3v) out_ to gnd .............................................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70 c) 16-pin tssop (derate 9.4mw/ c above +70 c) .........755mw 16-pin so (derate 8.7mw/ c above +70 c)................696mw storage temperature range .............................-65 c to +150 c maximum junction temperature .....................................+150 c operating temperature range ...........................-40 c to +85 c lead temperature (soldering, 10s) .................................+300 c esd protection (human body model, in_+, in_-) ....................................8kv MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, differential input voltage |v id | = 0.1v to 1.0v, common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|, t a = -40 c to +85 c. typical values are at v cc = +3.3v, t a = +25 c, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions min typ max units lvds inputs (in_+, in_-) differential input high threshold v th 100 mv differential input low threshold v tl -100 mv 0.1v ? v id ? 0.6v -20 20 a input current (MAX9121) i in _+, i in _- 0.6v MAX9121) i inoff 0.6v < ? v id ? 1.0v, v cc = 0 -25 25 a input resistor 1 r in1 v cc = 3.6v or 0, figure 1 35 k ? input resistor 2 r in2 v cc = 3.6v or 0, figure 1 132 k ? differential input resistance (max9122) r diff v cc = 3.6v or 0, figure 1 90 107 132 ? lvcmos/lvttl outputs (out_) open, undriven short, or undriven 100 ? parallel termination 2.7 3.2 i oh = -4.0ma (MAX9121) v id = +100mv 2.7 3.2 open or undriven short 2.7 3.2 output high voltage (table 1) v oh i oh = -4.0ma (max9122) v id = +100mv 2.7 3.2 v output low voltage v ol i ol = +4.0ma, v id = -100mv 0.1 0.25 v output short-circuit current i os enabled, v id = 0.1v, v out _ = 0 (note 2) -15 -120 ma output high-impedance current i oz disabled, v out = 0 or v cc -10 +10 a
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units logic inputs (en, en ) input high voltage v ih 2.0 v cc v input low voltage v il 0 0.8 v input current i in v in_ = v cc or 0 -15 15 a supply supply current i cc enabled, inputs open 9 15 ma disabled supply current i ccz disabled, inputs open 0.07 0.5 ma ac electrical characteristics (v cc = +3.0v to +3.6v, c l = 15pf, differential input voltage |v id | = 0.2v to 1.0v, common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100mhz, t a = -40 c to +85 c. typical values are at v cc = +3.3v, v cm = 1.2v, |v id | = 0.2v, t a = +25 c, unless otherwise noted.) (notes 3, 4) parameter symbol conditions min typ max units differential propagation delay high to low t phld figures 2 and 3 1.2 1.93 2.7 ns differential propagation delay low to high t plhd figures 2 and 3 1.2 1.79 2.7 ns differential pulse skew [t phld - t plhd ] (note 5) t skd1 figures 2 and 3 140 300 ps differential channel-to-channel skew (note 6) t skd2 figures 2 and 3 400 ps differential part-to-part skew (note 7) t skd3 figures 2 and 3 0.8 ns differential part-to-part skew (note 8) t skd4 figures 2 and 3 1.5 ns rise-time t tlh figures 2 and 3 0.55 1.0 ns fall-time t thl figures 2 and 3 0.54 1.0 ns disable time high to z t phz r l = 2k ? , figures 4 and 5 14 ns disable time low to z t plz r l = 2k ? , figures 4 and 5 14 ns enable time z to high t pzh r l = 2k ? , figures 4 and 5 70 ns enable time z to low t pzl r l = 2k ? , figures 4 and 5 70 ns maximum operating frequency (note 9) f max all channels switching 250 300 mhz dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, differential input voltage |v id | = 0.1v to 1.0v, common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|, t a = -40 c to +85 c. typical values are at v cc = +3.3v, t a = +25 c, unless otherwise noted.) (note 1)
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, v cm = +1.2v, |v id | = 0.2v, c l = 15pf, t a = +25 c, unless otherwise noted.) (figures 2 and 3) 40 0 0.01 0.1 1000 100 supply current vs. frequency 10 20 30 MAX9121/22 toc01 frequency (mhz) supply current (ma) 110 all channels switching one switching 7.00 7.50 8.00 8.50 9.00 9.50 10.00 10.50 11.00 -40 -15 10 35 60 85 supply current vs. temperature MAX9121/22 toc02 temperature ( c) supply current (ma) 0 10 30 20 40 50 3.0 3.3 3.6 differential threshold voltage vs. supply voltage MAX9121/22 toc03 supply voltage (v) differential threshold voltage (mv) note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v th , v tl , and v id . note 2: short only one output at a time. do not exceed the absolute maximum junction temperature specification. note 3: ac parameters are guaranteed by design and characterization. note 4: c l includes scope probe and test jig capacitance. note 5: t skd1 is the magnitude difference of differential propagation delays in a channel. t skd1 = |t phld - t plhd |. note 6: t skd2 is the magnitude difference of the t plhd or t phld of one channel and the t plhd or t phld of any other channel on the same part. note 7: t skd3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same v cc and within 5 c of each other. note 8: t skd4 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. note 9: f max generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, v oh = +1.3v, v ol = +1.1v, MAX9121/max9122 output criteria: 60% to 40% duty cycle, v ol = 0.4v (max), v oh = 2.7v (min), load = 15pf. 3.0 3.3 3.6 output short-circuit current vs. supply voltage MAX9121/22 toc04 supply voltage (v) output short-circuit current (ma) -70 -75 -80 -65 -90 -95 -85 1.30 1.25 1.20 1.15 1.10 3.0 3.3 3.6 output high-impedance current vs. supply voltage MAX9121/22 toc05 supply voltage (v) output high-impedance current (na) 2.7 2.9 3.3 3.1 3.5 3.7 3.0 3.3 3.6 output high voltage vs. supply voltage MAX9121/22 toc06 supply voltage (v) output high voltage (v) ac electrical characteristics (continued) (v cc = +3.0v to +3.6v, c l = 15pf, differential input voltage |v id | = 0.2v to 1.0v, common-mode voltage v cm = |v id /2| to 2.4v - |v id /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100mhz, t a = -40 c to +85 c. typical values are at v cc = +3.3v, v cm = 1.2v, |v id | = 0.2v, t a = +25 c, unless otherwise noted.) (notes 3, 4)
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v cc = +3.3v, v cm = +1.2v, |v id | = 0.2v, c l = 15pf, t a = +25 c, unless otherwise noted.) (figures 2 and 3) 600 575 550 525 500 3.0 3.3 3.6 transition time vs. supply voltage MAX9121/22 toc13 supply voltage (v) transition time (ps) t tlh t thl 450 475 500 525 550 575 600 625 650 -40 -15 10 35 60 85 transition time vs. temperature MAX9121/22 toc14 temperature ( c) transition time (ps) t tlh t thl 3.0 3.3 3.6 output low voltage vs. supply voltage MAX9121/22 toc07 supply voltage (v) output low voltage (mv) 93 94 95 96 97 92 99 100 98 1.60 1.80 1.70 2.00 1.90 2.10 2.20 3.0 3.3 3.6 differential propagation delay vs. supply voltage MAX9121/22 toc08 supply voltage (v) differential propagation delay (ns) t phld t plhd 1.50 1.70 1.90 2.10 -40 10 -15 35 60 85 differential propagation delay vs. temperature MAX9121/22 toc09 temperature ( c) differential propagation delay (ns) t phld t plhd 1.25 1.50 2.00 1.75 2.25 2.50 -0.5 0.5 0 1.0 1.5 2.0 2.5 differential propagation delay vs. common-mode voltage MAX9121/22 toc10 common-mode voltage (v) differential propagation delay (ns) t phld t plhd 1.5 1.7 1.6 1.9 1.8 2.1 2.0 2.2 100 900 1700 2500 differential propagation delay vs. differential input voltage MAX9121/22 toc11 differential input voltage (mv) differential propagation delay (ns) t phld t plhd 200 175 150 125 100 3.0 3.3 3.6 differential pulse skew vs. supply voltage MAX9121/22 toc12 supply voltage (v) differential pulse skew (ps)
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout 6 _______________________________________________________________________________________ detailed description the lvds interface standard is a signaling method intended for point-to-point communication over a con- trolled-impedance medium as defined by the ansi tia/eia-644 and ieee 1596.3 standards. the lvds stan- dard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing emi emissions and system susceptibility to noise. the MAX9121/max9122 are 500mbps, four-channel lvds receivers intended for high-speed, point-to-point, low-power applications. each channel accepts an lvds input and translates it to an lvttl/lvcmos out- put. the receiver is capable of detecting differential signals as low as 100mv and as high as 1v within an input voltage range of 0 to 2.4v. the 250mv to 400mv differential output of an lvds driver is nominally cen- tered around a +1.2v offset. this offset, coupled with the receiver s 0 to 2.4v input voltage range, allows an approximate 1v shift in the signal (as seen by the receiver). this allows for a difference in ground refer- ences of the transmitter and the receiver, the common- mode effects of coupled noise, or both. the lvds stan- dards specify an input voltage range of 0 to +2.4v referenced to receiver ground. the max9122 has an integrated termination resistor that is internally connected across each receiver input. the internal termination saves board space, eases lay- out, and reduces stub length compared to an external termination resistor. in other words, the transmission line is terminated on the ic. fail-safe the fail-safe feature of the MAX9121/max9122 sets an output high when: inputs are open. inputs are undriven and shorted. inputs are undriven and terminated. a fail-safe circuit is important because under these conditions, noise at the inputs may switch the receiver and it may appear to the system that data is being pin description pin name function 1, 4, 5, 8 in_- inverting differential receiver inputs 2, 3, 6, 7 in_+ noninverting differential receiver inputs 9, 16 en , en receiver enable inputs. when en = high and en = low or open, the outputs are active. for other combinations of en and en , the outputs are disabled and in high impedance. 10, 11, 14, 15 out_ lvcmos/lvttl receiver outputs 12 gnd ground 13 v cc power-supply input. bypass v cc to gnd with 0.1f and 0.001f ceramic capacitors. table 1. input/output function table enables inputs output en en (in_+) - (in_-) out_ v id +100mv h v id -100mv l MAX9121 open, undriven short, or undriven 100 ? parallel termination h l or open max9122 open or undriven short h all other combinations of enable pins don t care z
received. open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the lvds driver outputs are high impedance. a short condition can occur because of a cable failure. the fail-safe input network (figure 1) samples the input common-mode voltage and compares it to v cc - 0.3v (nominal). when the input is driven to levels specified in the lvds standards, the input to the common-mode voltage is less than v cc - 0.3v and the fail-safe circuit is not activated. if the inputs are open or if the inputs are undriven and shorted or undriven and parallel ter- minated, there is no input current. in this case, a pullup resistor in the fail-safe circuit pulls both inputs above v cc - 0.3v, activating the fail-safe circuit and forcing the output high. applications information power-supply bypassing bypass the v cc pin with high-frequency surface-mount ceramic 0.1f and 0.001f capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to v cc . differential traces input trace characteristics affect the performance of the MAX9121/max9122. use controlled-impedance pc board traces to match the cable characteristic imped- ance. the termination resistor is also matched to this characteristic impedance. eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. reduce skew by matching the electrical length of the traces. excessive skew can result in a degradation of magnetic field cancellation. each channel s differential signals should be routed close to each other to cancel their external magnetic field. maintain a constant distance between the differ- ential traces to avoid discontinuities in differential impedance. avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities. MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout _______________________________________________________________________________________ 7 in_+ v cc - 0.3v in_- out_ MAX9121 max9122 r in2 v cc r in1 r in1 in_+ v cc - 0.3v in_- out_ r in2 v cc r in1 r diff r in1 figure 1. input with fail-safe network
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout 8 _______________________________________________________________________________________ cables and connectors transmission media typically have a controlled differen- tial impedance of 100 ? . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. avoid the use of unbalanced cables such as ribbon or simple coaxial cable. balanced cables such as twisted pair offer superior signal quality and tend to generate less emi due to magnetic field canceling effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver. termination the max9122 has an integrated termination resistor connected across the inputs of each receiver. the value of the integrated resistor is specified in the dc characteristics. the MAX9121 requires an external termination resistor. the termination resistor should match the differential impedance of the transmission line. termination resis- tance values may range between 90 ? to 132 ? , depending on the characteristic impedance of the transmission medium. when using the MAX9121, minimize the distance between the input termination resistors and the MAX9121 receiver inputs. use 1% surface-mount resis- tors. in_+ in_- out_ receiver enabled 1/4 MAX9121/max9122 50 ? required for pulse generator. when testing the max9122, adjust the pulse generator output to account for internal termination resistor. * ** pulse generator** 50 ? *50 ? * c l figure 2. propagation delay and transition time test circuit figure 3. propagation delay and transition time waveforms in_- in_+ out_ 50% v id v ol v oh v id = 0 20% 20% 80% 80% t phld t plhd t thl t tlh v id = 0 50% v id = (v in_+ ) - (v in_- ) note : v cm = (v in- + v in+ ) 2
board layout because the MAX9121/max9122 feature a flow-through pinout, no special layout precautions are required. keep the lvds and any other digital signals separated from each other to reduce crosstalk. for lvds applications, a four-layer pc board that pro- vides separate power, ground, lvds signals, and input signals is recommended. isolate the input lvds signals from each other to prevent coupling. isolate the output lvcmos/lvttl signals from each other to prevent coupling. separate the input lvds signals from the out- put signals planes with the power and ground planes for best results. MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout _______________________________________________________________________________________ 9 in_+ en en in_- out_ device under test 1/4 MAX9121/max9122 c l includes load and test jig capacitance. s 1 = v cc for t pzl and t plz measurements. s 1 = gnd for t pzh and t phz measurements. generator 50 ? c l r l s 1 v cc figure 4. high-impedance delay test circuit figure 5. high-impedance delay waveforms 1.5v en when en = gnd or open en when en = v cc output when v id = -100mv output when v id = +100mv 1.5v 1.5v 0.5v 0.5v t plz t phz t pzl t pzh 1.5v 3v 0 3v v cc v ol v oh gnd 0 50% 50% chip information transistor count: 1354 process: cmos
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout 10 ______________________________________________________________________________________ functional diagram 107 ? in1+ in1- in2+ in2- in3+ in3- in4+ in4- en en out1 out2 out3 out4 MAX9121 max9122 107 ? 107 ? 107 ? gnd v cc in1+ in1- in2+ in2- in3+ in3- in4+ in4- en en out1 out2 out3 out4 gnd v cc pin configuration 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1- en out1 out2 v cc gnd out3 out4 en top view MAX9121 max9122 tssop/so in1+ in2+ in3+ in2- in3- in4+ in4-
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout ______________________________________________________________________________________ 11 package information tssop,no pads.eps
MAX9121/max9122 quad lvds line receivers with integrated termination and flow-through pinout maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. soicn.eps package information (continued)

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